Well known RAMs have at least one address port and include storage elements (core cells). In a paper by A. L. Silburt et al entitled "A180-MHz 0.8-.mu.m BiCMOS Modular Memory Family of DRAM and Multiport SRAM", IEEE Journal of Solid-State Circuits, Vol. 28, No. 3, Mar. 1993, p. 222, at 227 and 228 show various RAM core arrays.
It is a problem to develop a practical, high-speed, low-power and area efficient core cell to support multiple ports (e.g., a single high-speed write port and four high-speed read ports). A conventional five port cell would have required additional access lines and significant area to achieve adequate stability margins.
In a paper by G. Gerosa et al entitled "A 2.2 W, 80 MHz Superscalar RISC Microprocessor", IEEE Journal of Solid-State Circuits, Vol., 29, No. 12, December 1994, p.1440, at 1447 shows a RAM storage element with single-ended write access structure. The disclosed structure of five ports (one write port and four read ports) includes a plurality of transistor stacks which are connected to respective bit lines. Each transistor stack has top and bottom MOSFETs (metal oxide semiconductor field effect transistors). The drain-source circuits of the top and bottom MOSFETs are series-connected. The gates of the bottom MOSFETs are connected to respective read port lines. The gates of all top MOSFETs are in parallel connected to the core cell. This results in unnecessary loading on the bit line, since the full MOSFET channel capacitance and internal diffusion capacitance of the top MOSFET in the stack is added to the bit line load for every core cell storing data which will set the gate of the top MOSFET "high". This may as much as double the bit line load, resulting in significantly reduced performance. Furthermore, the implementation described in the paper uses only single-ended read access which, for all but the smallest memories, may result in substantially inferior read performance.
U.S. Pat. No. 4,958,322 granted to Kosugi et al on Sep. 18, 1990 discloses a pseudo memory device wherein DRAM (dynamic random access memory) is operated to function as an SRAM.